Thin film inductors are widely used in integrated circuits. Usually planar inductors of rectangular, octagonal or circular layout are used, since these are easy to manufacture, having regard to the often very small dimensions required. Inductors are often provided in microwave monolithic integrated circuits, MMIC's. Certain requirements apply to inductors in MMIC's because of the semiconductor substrates used for fabricating such devices.
A particular problem is that losses occur for inductors, which are formed on low resistivity or lossy substrate materials.
Losses in the inductors can be overcome by using semiconductor substrates such as GaAs or other high resistivity substrates having a resistivity p&gt;100 .OMEGA.m, but these substrate materials are relatively expensive.
Silicon on the other hand, which has many excellent properties including a relatively low price, is not an ideal substrate material for inductors because of its lossy properties ranging in the area of 0,0001-20 .OMEGA.m. The relatively low resistance of the material leads to eddy currents being generated in the substrate, which then again lead to losses occurring in the inductor.
The losses for a given inductor can be expressed by means of the so-called Q-factor, which in a simple case may be regarded as the ratio of the conserved magnetic energy to the losses. it can be represented as
Q=(.omega.L/r) (I)
where L is the inductance of the coil, r is the resistance taking into account the losses and .omega. is the circular frequency. At microwave frequencies, the total losses are given by ohmic resistance to the currents flowing in the strips and the dielectric losses in the surrounding dielectrics, such as the substrate. The losses and the overall performance of the inductance depend not only on the geometry and materials involved but also on the way the inductors are coupled in the actual application. These effects shall be dealt with briefly in the following by reference to appropriate models for an inductor.
A planar inductor usually has two terminals relating to the conductive pattern provided on the face of the substrate and it may have a ground plane arranged on the opposite face, the ground plane being provided with one or more terminals.
FIG. 1 shows a known inductor having a simple loop structure being arranged on a dielectric or semiconductor substrate and having an optional ground plane being provided on the opposite side of the substrate. FIG. 2 is a cross-sectional view of the inductor shown on FIG. 1.
FIG. 3 relates to a known meander structure, which requires a ground plane for the return current. FIG. 4 is a cross-sectional view of the inductor shown on FIG. 3.
The terminals of the inductors can be coupled in various combinations. FIGS. 5, 6 and 7 depicts three main models corresponding to different ways of coupling the inductor and optionally arranging the ground plane for the plane inductors such as those shown in FIGS. 1-4.
In FIG. 5 the inductor has a ground plane and is coupled as a two port, that is, the input terminals are formed between the terminal strip and the ground plane and the output port is formed between the terminal relating to the other end of the strip and the terminal of the adjacent ground plane.
In the FIG. 5 configuration, return currents are flowing through the ground plane and a parasitic capacitance Cp and resistance Rp exist between the inductor strips and the ground plane. r.sub.strip represents the losses in the strips and the losses in the ground plane. Additional ohmic losses (free carrier absorption) appear if the substrate is made of a semiconductor with free-charge carriers. These free carriers cause substrate currents between points of the strips having a potential difference (cf. FIG. 2). The losses associated therewith are represented by the shunt loss resistance Rs. Cs is the parasitic capacitance due to the capacitive coupling between the strips and through the dielectric substrate. Finally, the losses relating to the parasitic currents, which are shown in FIG. 1a with dotted arrows being of opposite direction to the main strip currents, are represented by the losses in r.sub.substr in the model according to FIG. 5.
FIG. 6 shows a one-port configuration, whereby the inductor is provided with a ground plane on the backside of the substrate and whereby the output port has been shorted. The components correspond to those shown in FIG. 5 (In this coupling, return current is flowing in the ground?).
For the inductor shown in FIG. 7, no ground plane has been provided or none of the strip terminals have been grounded. In this case, there is no parasitic capacitance Cp and no parasitic resistance Rp.
It can be demonstrated that in many cases the inductor configurations shown on FIGS. 5-7 may be transformed to the more simplified circuit shown on FIG. 8.
It should be noted that using the simplified equivalent of FIG. 8 for the FIG. 7 arrangement, R equals Rs, C equals Cs and r equals r.sub.substr +r.sub.strip. Correspondingly, it can be shown that the parameters of the simplified equivalent of FIG. 8 can also be expressed by means of values calculated on the basis of the parameters given according to FIGS. 5 and 6.
According to prior art document "On-chip Spiral Inductors With Patterned Ground Shields for Si Based RFICs", by Yue et al, IEEE Journ. Solid State electronics, vol. 33, no5, pp.743, (year?)(D1) the Q-factor according to the above simplified embodiment may be given as: ##EQU1##
In the above expression, R equals Rs, while r equals r.sub.substr +r.sub.strip.
Several proposals have been put forward in the past for reducing substrate currents in lossy substrates in order to increase the Q-value.
Many proposals are based on performing changes in the substrate so as to transform the resistances r and R. In document U.S. Pat. No. 5,757,243 (D2) an inductor has been shown, whereby low and high resistivity layers are formed in the substrate by diffusion or other relevant techniques in order to reduce the substrate currents.
Prior art document "Reducing the substrate losses of RF Integrated Inductors", Mernyei et al., IEEE Microwave and Guided Wave Letters, Vol. 8, No 9, pp. 300,1998 (D3), discloses a spiral planar inductor, which has been shown in FIGS. 9 and 10 of this patent application. The inductor according to the above document has a star shaped blocking structure, 2, embedded in the substrate, having layers denoted by reference numerals 4-7.
For the inductor according to prior art document D1 mentioned above, slots are provided in the low resistivity substrate under the inductor in order to reduce circumferential currents.
According to prior art document "Large suspended Inductors on Silicon and Their Use in a 2 .mu.m CMOS RF amplifier", by J. Y. C. Chang, IEEE Electron Device Letters, Vol. 14, No. 5, pp. 246, May 1993 (D4) the silicon substrate underneath specific strips in the inductor structure has been removed by under-etching.
The above techniques, however, require additional masks and technological processes, are therefore costly to very costly, and are not practical for large-scale industrial application.
According to JP-A-06 224 042 (D5), a planar inductor has been disclosed comprising two magnetic wafers separated by a glass film, one wafer having slots in the shape of a meander, which enables the formation of a copper inductor being formed adjacent the glass film. The structure of the inductor according to this document has a set of input terminals being arranged close together. The inductor is claimed to provide enhanced high frequency characteristics and a high quality factor value. However, the wafers, which are made of nickel-zinc ferrite, have a high resistance factor. Moreover, the inductor does not appear suitable for the microwave range of above 300 Mhz and substantial losses in this range are expected. The inductor according to D5 requires a complex manufacturing technique, which is incompatible with MMIC manufacture.
In prior art document "A Q-factor enhancement technique for MMIC inductors", by M. Danesh et al., IEEE MTT-S Digest, 5/1998 (D6) a square spiral microstrip inductor fabricated in a production silicon IC technology has been disclosed.
According to document D6, it has been shown that driving the microstrip structure differentially yields a significantly higher Q-factor as compared to driving the structure "single ended", i.e. connecting the source to one terminal while connecting the other terminal to ground.